A         |      ;:&kDec  6 202318:11:30HOST64sm_86//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-31833905
// Cuda compilation tools, release 11.8, V11.8.89
// Based on NVVM 7.0.1
//

.version 7.8
.target sm_50
.address_size 64

	// .globl	ThresholdLookupAlphaKernel
.const .align 4 .b8 kRGB32f_To_601YPbPr[36] = {135, 22, 153, 62, 162, 69, 22, 63, 213, 120, 233, 61, 33, 201, 44, 190, 111, 155, 169, 190, 0, 0, 0, 63, 0, 0, 0, 63, 70, 94, 214, 190, 232, 134, 166, 189};
.const .align 4 .b8 k601YPbPr_To_RGB32f[36] = {0, 0, 128, 63, 0, 0, 0, 0, 188, 116, 179, 63, 0, 0, 128, 63, 152, 50, 176, 190, 158, 209, 54, 191, 0, 0, 128, 63, 229, 208, 226, 63, 0, 0, 0, 0};
.const .align 4 .b8 kRGB32f_To_601YCbCr[36] = {70, 246, 130, 66, 145, 141, 0, 67, 94, 186, 199, 65, 33, 48, 23, 194, 240, 103, 148, 194, 0, 0, 224, 66, 0, 0, 224, 66, 111, 146, 187, 194, 70, 182, 145, 193};
.const .align 4 .b8 k601YCbCr_To_RGB32f[36] = {37, 160, 149, 59, 0, 0, 0, 0, 182, 23, 205, 59, 37, 160, 149, 59, 40, 15, 201, 186, 156, 239, 80, 187, 37, 160, 149, 59, 236, 155, 1, 60, 0, 0, 0, 0};
.const .align 4 .b8 kRGB8u_To_601YCbCr[36] = {219, 121, 131, 62, 152, 14, 1, 63, 18, 131, 200, 61, 174, 199, 23, 190, 238, 252, 148, 190, 197, 224, 224, 62, 197, 224, 224, 62, 217, 78, 188, 190, 174, 71, 146, 189};
.const .align 4 .b8 k601YCbCr_To_RGB8u[36] = {127, 10, 149, 63, 0, 0, 0, 0, 160, 74, 204, 63, 127, 10, 149, 63, 254, 148, 200, 190, 184, 30, 80, 191, 127, 10, 149, 63, 78, 26, 1, 64, 0, 0, 0, 0};
.const .align 4 .b8 kRGB8u_To_601YCbCrFullRange[36] = {135, 22, 153, 62, 162, 69, 22, 63, 213, 120, 233, 61, 166, 27, 44, 190, 39, 241, 168, 190, 250, 254, 254, 62, 250, 254, 254, 62, 43, 135, 213, 190, 59, 223, 165, 189};
.const .align 4 .b8 k601YCbCrFullRange_To_RGB8u[36] = {0, 0, 128, 63, 0, 0, 0, 0, 72, 193, 178, 63, 0, 0, 128, 63, 143, 130, 175, 190, 225, 26, 54, 191, 0, 0, 128, 63, 20, 238, 225, 63, 0, 0, 0, 0};
.const .align 4 .b8 kRGB32f_To_601YCbCrFullRange[36] = {113, 125, 152, 66, 92, 175, 21, 67, 92, 143, 232, 65, 158, 111, 43, 194, 49, 72, 168, 194, 0, 0, 254, 66, 0, 0, 254, 66, 170, 177, 212, 194, 88, 57, 165, 193};
.const .align 4 .b8 k601YCbCrFullRange_To_RGB32f[36] = {129, 128, 128, 59, 0, 0, 0, 0, 189, 116, 179, 59, 129, 128, 128, 59, 194, 50, 176, 186, 179, 209, 54, 187, 129, 128, 128, 59, 229, 208, 226, 59, 0, 0, 0, 0};
.const .align 4 .b8 kRGB32f_To_709YPbPr[36] = {208, 179, 89, 62, 89, 23, 55, 63, 152, 221, 147, 61, 186, 164, 234, 189, 210, 86, 197, 190, 0, 0, 0, 63, 0, 0, 0, 63, 190, 134, 232, 190, 16, 202, 59, 189};
.const .align 4 .b8 k709YPbPr_To_RGB32f[36] = {0, 0, 128, 63, 0, 0, 0, 0, 12, 147, 201, 63, 0, 0, 128, 63, 221, 209, 63, 190, 243, 173, 239, 190, 0, 0, 128, 63, 77, 132, 237, 63, 0, 0, 0, 0};
.const .align 4 .b8 kRGB32f_To_709YCbCr[36] = {106, 60, 58, 66, 6, 161, 28, 67, 244, 253, 124, 65, 223, 79, 205, 193, 8, 172, 172, 194, 0, 0, 224, 66, 0, 0, 224, 66, 195, 117, 203, 194, 236, 81, 36, 193};
.const .align 4 .b8 k709YCbCr_To_RGB32f[36] = {37, 160, 149, 59, 0, 0, 0, 0, 239, 94, 230, 59, 37, 160, 149, 59, 33, 57, 91, 186, 178, 245, 8, 187, 37, 160, 149, 59, 82, 185, 7, 60, 0, 0, 0, 0};
.const .align 4 .b8 k709YCbCrFullRange_To_RGB32f[36] = {131, 128, 128, 59, 0, 0, 0, 0, 28, 147, 201, 59, 131, 128, 128, 59, 61, 210, 63, 186, 248, 173, 239, 186, 131, 128, 128, 59, 82, 132, 237, 59, 0, 0, 0, 0};
.const .align 4 .b8 kRGB8u_To_709YCbCr[36] = {207, 247, 58, 62, 53, 62, 29, 63, 231, 251, 125, 61, 184, 30, 206, 189, 23, 89, 173, 190, 197, 224, 224, 62, 197, 224, 224, 62, 12, 66, 204, 190, 195, 245, 36, 189};
.const .align 4 .b8 k709YCbCr_To_RGB8u[36] = {127, 10, 149, 63, 0, 0, 0, 0, 147, 120, 229, 63, 127, 10, 149, 63, 53, 94, 90, 190, 205, 108, 8, 191, 127, 10, 149, 63, 154, 49, 7, 64, 0, 0, 0, 0};
.const .align 4 .b8 k709YCbCr_To_601YCbCr[36] = {0, 0, 128, 63, 23, 100, 203, 61, 1, 77, 68, 62, 0, 0, 0, 0, 18, 103, 125, 63, 10, 158, 226, 189, 0, 0, 0, 0, 61, 98, 148, 189, 249, 191, 123, 63};
.const .align 4 .b8 k601YCbCr_To_709YCbCr[36] = {0, 0, 128, 63, 122, 165, 236, 189, 179, 237, 84, 190, 0, 0, 0, 0, 204, 98, 130, 63, 216, 188, 234, 61, 0, 0, 0, 0, 74, 179, 153, 61, 234, 61, 131, 63};
.const .align 4 .b8 kZeroMatrix[36];
.const .align 4 .b8 kYCbCrOffset[12] = {0, 0, 128, 65, 0, 0, 0, 67, 0, 0, 0, 67};
.const .align 4 .b8 kYCbCrFullRangeOffset[12] = {0, 0, 0, 0, 0, 0, 0, 67, 0, 0, 0, 67};
.const .align 4 .f32 PQ_m1 = 0f3E232000;
.const .align 4 .f32 PQ_m1Inv = 0f40C8E06B;
.const .align 4 .f32 PQ_m2 = 0f429DB000;
.const .align 4 .f32 PQ_m2Inv = 0f3C4FCDAC;
.const .align 4 .f32 PQ_c1 = 0f3F560000;
.const .align 4 .f32 PQ_c2 = 0f4196D000;
.const .align 4 .f32 PQ_c3 = 0f41958000;
.const .align 4 .f32 Gamma1886 = 0f4019999A;
.const .align 4 .f32 PQ_Lpeak = 0f461C4000;
.const .align 4 .f32 PQ_a = 0f3F8CAC08;
.const .align 4 .f32 PQ_b = 0f426E1556;
.const .align 4 .f32 PQ_c = 0f39B033E5;
.const .align 4 .f32 PQ_s = 0f4385EB85;
.const .align 4 .f32 PQ_g = 0f3EE66666;
.const .align 4 .f32 scaleFD = 0f42C80000;
.const .align 4 .f32 HLG_a = 0f3E371FF0;
.const .align 4 .f32 HLG_b = 0f3E91C020;
.const .align 4 .f32 HLG_c = 0f3F0F564F;
.const .align 4 .f32 HLG_inva = 0f40B2F029;
.const .align 4 .f32 HLG_alpha = 0f41200000;
.const .align 4 .f32 HLG_invAlpha = 0f3DCCCCCD;
.const .align 4 .f32 HLG_gamma = 0f3F99999A;
.const .align 4 .f32 HLG_gammaM1 = 0f3E4CCCCD;
.const .align 4 .f32 HLG_gammaM1Dgamma = 0f3E2AAAAB;
.const .align 4 .f32 HLG_YR = 0f3E86809D;
.const .align 4 .f32 HLG_YG = 0f3F2D9168;
.const .align 4 .f32 HLG_YB = 0f3D72E48F;
.const .align 4 .f32 HLG_Lpeak = 0f447A0000;
.global .texref inRGBALUT;
.global .texref inMLUT;
.const .align 4 .f32 kMinAlphaValue = 0f24E69595;

.visible .entry ThresholdLookupAlphaKernel(
	.param .u64 ThresholdLookupAlphaKernel_param_0,
	.param .u64 ThresholdLookupAlphaKernel_param_1,
	.param .u32 ThresholdLookupAlphaKernel_param_2,
	.param .u32 ThresholdLookupAlphaKernel_param_3,
	.param .u32 ThresholdLookupAlphaKernel_param_4,
	.param .u32 ThresholdLookupAlphaKernel_param_5,
	.param .u32 ThresholdLookupAlphaKernel_param_6,
	.param .f32 ThresholdLookupAlphaKernel_param_7,
	.param .f32 ThresholdLookupAlphaKernel_param_8,
	.param .u32 ThresholdLookupAlphaKernel_param_9
)
{
	.reg .pred 	%p<8>;
	.reg .b16 	%rs<9>;
	.reg .f32 	%f<20>;
	.reg .b32 	%r<16>;
	.reg .b64 	%rd<15>;


	ld.param.u64 	%rd5, [ThresholdLookupAlphaKernel_param_0];
	ld.param.u64 	%rd6, [ThresholdLookupAlphaKernel_param_1];
	ld.param.u32 	%r3, [ThresholdLookupAlphaKernel_param_2];
	ld.param.u32 	%r4, [ThresholdLookupAlphaKernel_param_3];
	ld.param.u32 	%r5, [ThresholdLookupAlphaKernel_param_4];
	ld.param.u32 	%r6, [ThresholdLookupAlphaKernel_param_5];
	ld.param.u32 	%r7, [ThresholdLookupAlphaKernel_param_6];
	ld.param.f32 	%f5, [ThresholdLookupAlphaKernel_param_7];
	ld.param.f32 	%f6, [ThresholdLookupAlphaKernel_param_8];
	cvta.to.global.u64 	%rd1, %rd6;
	cvta.to.global.u64 	%rd2, %rd5;
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r10, %tid.x;
	mad.lo.s32 	%r1, %r9, %r8, %r10;
	mov.u32 	%r11, %ntid.y;
	mov.u32 	%r12, %ctaid.y;
	mov.u32 	%r13, %tid.y;
	mad.lo.s32 	%r2, %r12, %r11, %r13;
	setp.ge.s32 	%p1, %r1, %r6;
	setp.ge.s32 	%p2, %r2, %r7;
	or.pred  	%p3, %p1, %p2;
	@%p3 bra 	$L__BB0_7;

	mad.lo.s32 	%r14, %r2, %r3, %r1;
	cvt.s64.s32 	%rd3, %r14;
	setp.eq.s32 	%p4, %r5, 0;
	@%p4 bra 	$L__BB0_3;

	shl.b64 	%rd7, %rd3, 4;
	add.s64 	%rd8, %rd2, %rd7;
	ld.global.f32 	%f19, [%rd8+12];
	bra.uni 	$L__BB0_4;

$L__BB0_3:
	shl.b64 	%rd9, %rd3, 3;
	add.s64 	%rd10, %rd2, %rd9;
	ld.global.u16 	%rs4, [%rd10+6];
	// begin inline asm
	{  cvt.f32.f16 %f19, %rs4;}

	// end inline asm

$L__BB0_4:
	sub.ftz.f32 	%f11, %f19, %f5;
	mul.ftz.f32 	%f12, %f11, %f6;
	setp.lt.ftz.f32 	%p5, %f19, %f5;
	selp.f32 	%f13, 0f00000000, %f12, %p5;
	setp.gt.ftz.f32 	%p6, %f13, 0f3F800000;
	selp.f32 	%f4, 0f3F800000, %f13, %p6;
	mad.lo.s32 	%r15, %r2, %r4, %r1;
	cvt.s64.s32 	%rd4, %r15;
	@%p4 bra 	$L__BB0_6;

	shl.b64 	%rd11, %rd4, 4;
	add.s64 	%rd12, %rd1, %rd11;
	mov.f32 	%f14, 0f00000000;
	st.global.v4.f32 	[%rd12], {%f14, %f14, %f14, %f4};
	bra.uni 	$L__BB0_7;

$L__BB0_6:
	mov.f32 	%f17, 0f00000000;
	// begin inline asm
	{  cvt.rn.f16.f32 %rs5, %f17;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs6, %f17;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs7, %f17;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs8, %f4;}

	// end inline asm
	shl.b64 	%rd13, %rd4, 3;
	add.s64 	%rd14, %rd1, %rd13;
	st.global.u16 	[%rd14], %rs5;
	st.global.u16 	[%rd14+2], %rs6;
	st.global.u16 	[%rd14+4], %rs7;
	st.global.u16 	[%rd14+6], %rs8;

$L__BB0_7:
	ret;

}
	// .globl	ThresholdLookupRGBKernel
.visible .entry ThresholdLookupRGBKernel(
	.param .u64 ThresholdLookupRGBKernel_param_0,
	.param .u64 ThresholdLookupRGBKernel_param_1,
	.param .u32 ThresholdLookupRGBKernel_param_2,
	.param .u32 ThresholdLookupRGBKernel_param_3,
	.param .u32 ThresholdLookupRGBKernel_param_4,
	.param .u32 ThresholdLookupRGBKernel_param_5,
	.param .u32 ThresholdLookupRGBKernel_param_6,
	.param .f32 ThresholdLookupRGBKernel_param_7,
	.param .f32 ThresholdLookupRGBKernel_param_8,
	.param .u32 ThresholdLookupRGBKernel_param_9
)
{
	.reg .pred 	%p<10>;
	.reg .b16 	%rs<9>;
	.reg .f32 	%f<49>;
	.reg .b32 	%r<17>;
	.reg .b64 	%rd<15>;


	ld.param.u64 	%rd5, [ThresholdLookupRGBKernel_param_0];
	ld.param.u64 	%rd6, [ThresholdLookupRGBKernel_param_1];
	ld.param.u32 	%r3, [ThresholdLookupRGBKernel_param_2];
	ld.param.u32 	%r4, [ThresholdLookupRGBKernel_param_3];
	ld.param.u32 	%r5, [ThresholdLookupRGBKernel_param_4];
	ld.param.u32 	%r7, [ThresholdLookupRGBKernel_param_5];
	ld.param.u32 	%r8, [ThresholdLookupRGBKernel_param_6];
	ld.param.f32 	%f22, [ThresholdLookupRGBKernel_param_7];
	ld.param.f32 	%f23, [ThresholdLookupRGBKernel_param_8];
	ld.param.u32 	%r6, [ThresholdLookupRGBKernel_param_9];
	cvta.to.global.u64 	%rd1, %rd6;
	cvta.to.global.u64 	%rd2, %rd5;
	mov.u32 	%r9, %ntid.x;
	mov.u32 	%r10, %ctaid.x;
	mov.u32 	%r11, %tid.x;
	mad.lo.s32 	%r1, %r10, %r9, %r11;
	mov.u32 	%r12, %ntid.y;
	mov.u32 	%r13, %ctaid.y;
	mov.u32 	%r14, %tid.y;
	mad.lo.s32 	%r2, %r13, %r12, %r14;
	setp.ge.s32 	%p1, %r1, %r7;
	setp.ge.s32 	%p2, %r2, %r8;
	or.pred  	%p3, %p1, %p2;
	@%p3 bra 	$L__BB1_9;

	mad.lo.s32 	%r15, %r2, %r3, %r1;
	cvt.s64.s32 	%rd3, %r15;
	setp.eq.s32 	%p4, %r5, 0;
	@%p4 bra 	$L__BB1_3;

	shl.b64 	%rd7, %rd3, 4;
	add.s64 	%rd8, %rd2, %rd7;
	ld.global.v4.f32 	{%f42, %f43, %f44, %f45}, [%rd8];
	bra.uni 	$L__BB1_4;

$L__BB1_3:
	shl.b64 	%rd9, %rd3, 3;
	add.s64 	%rd10, %rd2, %rd9;
	ld.global.u16 	%rs1, [%rd10];
	ld.global.u16 	%rs2, [%rd10+2];
	ld.global.u16 	%rs3, [%rd10+4];
	ld.global.u16 	%rs4, [%rd10+6];
	// begin inline asm
	{  cvt.f32.f16 %f42, %rs1;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f43, %rs2;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f44, %rs3;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f45, %rs4;}

	// end inline asm

$L__BB1_4:
	sub.ftz.f32 	%f32, %f44, %f22;
	mul.ftz.f32 	%f33, %f32, %f23;
	setp.lt.ftz.f32 	%p5, %f44, %f22;
	selp.f32 	%f46, 0f00000000, %f33, %p5;
	sub.ftz.f32 	%f34, %f43, %f22;
	mul.ftz.f32 	%f35, %f34, %f23;
	setp.lt.ftz.f32 	%p6, %f43, %f22;
	selp.f32 	%f47, 0f00000000, %f35, %p6;
	sub.ftz.f32 	%f36, %f42, %f22;
	mul.ftz.f32 	%f37, %f36, %f23;
	setp.lt.ftz.f32 	%p7, %f42, %f22;
	selp.f32 	%f48, 0f00000000, %f37, %p7;
	setp.eq.s32 	%p8, %r6, 0;
	@%p8 bra 	$L__BB1_6;

	cvt.ftz.sat.f32.f32 	%f46, %f46;
	cvt.ftz.sat.f32.f32 	%f47, %f47;
	cvt.ftz.sat.f32.f32 	%f48, %f48;

$L__BB1_6:
	mad.lo.s32 	%r16, %r2, %r4, %r1;
	cvt.s64.s32 	%rd4, %r16;
	@%p4 bra 	$L__BB1_8;

	shl.b64 	%rd11, %rd4, 4;
	add.s64 	%rd12, %rd1, %rd11;
	st.global.v4.f32 	[%rd12], {%f48, %f47, %f46, %f45};
	bra.uni 	$L__BB1_9;

$L__BB1_8:
	// begin inline asm
	{  cvt.rn.f16.f32 %rs5, %f48;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs6, %f47;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs7, %f46;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs8, %f45;}

	// end inline asm
	shl.b64 	%rd13, %rd4, 3;
	add.s64 	%rd14, %rd1, %rd13;
	st.global.u16 	[%rd14], %rs5;
	st.global.u16 	[%rd14+2], %rs6;
	st.global.u16 	[%rd14+4], %rs7;
	st.global.u16 	[%rd14+6], %rs8;

$L__BB1_9:
	ret;

}
	// .globl	ThresholdLookupLuminanceKernel
.visible .entry ThresholdLookupLuminanceKernel(
	.param .u64 ThresholdLookupLuminanceKernel_param_0,
	.param .u64 ThresholdLookupLuminanceKernel_param_1,
	.param .u32 ThresholdLookupLuminanceKernel_param_2,
	.param .u32 ThresholdLookupLuminanceKernel_param_3,
	.param .u32 ThresholdLookupLuminanceKernel_param_4,
	.param .u32 ThresholdLookupLuminanceKernel_param_5,
	.param .u32 ThresholdLookupLuminanceKernel_param_6,
	.param .f32 ThresholdLookupLuminanceKernel_param_7,
	.param .f32 ThresholdLookupLuminanceKernel_param_8,
	.param .u32 ThresholdLookupLuminanceKernel_param_9
)
{
	.reg .pred 	%p<8>;
	.reg .b16 	%rs<9>;
	.reg .f32 	%f<39>;
	.reg .b32 	%r<16>;
	.reg .b64 	%rd<15>;


	ld.param.u64 	%rd5, [ThresholdLookupLuminanceKernel_param_0];
	ld.param.u64 	%rd6, [ThresholdLookupLuminanceKernel_param_1];
	ld.param.u32 	%r3, [ThresholdLookupLuminanceKernel_param_2];
	ld.param.u32 	%r4, [ThresholdLookupLuminanceKernel_param_3];
	ld.param.u32 	%r5, [ThresholdLookupLuminanceKernel_param_4];
	ld.param.u32 	%r6, [ThresholdLookupLuminanceKernel_param_5];
	ld.param.u32 	%r7, [ThresholdLookupLuminanceKernel_param_6];
	ld.param.f32 	%f14, [ThresholdLookupLuminanceKernel_param_7];
	ld.param.f32 	%f15, [ThresholdLookupLuminanceKernel_param_8];
	cvta.to.global.u64 	%rd1, %rd6;
	cvta.to.global.u64 	%rd2, %rd5;
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r10, %tid.x;
	mad.lo.s32 	%r1, %r9, %r8, %r10;
	mov.u32 	%r11, %ntid.y;
	mov.u32 	%r12, %ctaid.y;
	mov.u32 	%r13, %tid.y;
	mad.lo.s32 	%r2, %r12, %r11, %r13;
	setp.ge.s32 	%p1, %r1, %r6;
	setp.ge.s32 	%p2, %r2, %r7;
	or.pred  	%p3, %p1, %p2;
	@%p3 bra 	$L__BB2_7;

	mad.lo.s32 	%r14, %r2, %r3, %r1;
	cvt.s64.s32 	%rd3, %r14;
	setp.eq.s32 	%p4, %r5, 0;
	@%p4 bra 	$L__BB2_3;

	shl.b64 	%rd7, %rd3, 4;
	add.s64 	%rd8, %rd2, %rd7;
	ld.global.v4.f32 	{%f35, %f36, %f37, %f38}, [%rd8];
	bra.uni 	$L__BB2_4;

$L__BB2_3:
	shl.b64 	%rd9, %rd3, 3;
	add.s64 	%rd10, %rd2, %rd9;
	ld.global.u16 	%rs1, [%rd10];
	ld.global.u16 	%rs2, [%rd10+2];
	ld.global.u16 	%rs3, [%rd10+4];
	ld.global.u16 	%rs4, [%rd10+6];
	// begin inline asm
	{  cvt.f32.f16 %f35, %rs1;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f36, %rs2;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f37, %rs3;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f38, %rs4;}

	// end inline asm

$L__BB2_4:
	mul.ftz.f32 	%f24, %f37, 0f3E991687;
	fma.rn.ftz.f32 	%f25, %f36, 0f3F1645A2, %f24;
	fma.rn.ftz.f32 	%f26, %f35, 0f3DE978D5, %f25;
	mul.ftz.f32 	%f27, %f38, %f26;
	setp.lt.ftz.f32 	%p5, %f27, %f14;
	sub.ftz.f32 	%f28, %f27, %f14;
	mul.ftz.f32 	%f29, %f28, %f15;
	selp.f32 	%f30, 0f00000000, %f29, %p5;
	setp.gt.ftz.f32 	%p6, %f30, 0f3F800000;
	selp.f32 	%f13, 0f3F800000, %f30, %p6;
	mad.lo.s32 	%r15, %r2, %r4, %r1;
	cvt.s64.s32 	%rd4, %r15;
	@%p4 bra 	$L__BB2_6;

	shl.b64 	%rd11, %rd4, 4;
	add.s64 	%rd12, %rd1, %rd11;
	st.global.v4.f32 	[%rd12], {%f35, %f36, %f37, %f13};
	bra.uni 	$L__BB2_7;

$L__BB2_6:
	// begin inline asm
	{  cvt.rn.f16.f32 %rs5, %f35;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs6, %f36;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs7, %f37;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs8, %f13;}

	// end inline asm
	shl.b64 	%rd13, %rd4, 3;
	add.s64 	%rd14, %rd1, %rd13;
	st.global.u16 	[%rd14], %rs5;
	st.global.u16 	[%rd14+2], %rs6;
	st.global.u16 	[%rd14+4], %rs7;
	st.global.u16 	[%rd14+6], %rs8;

$L__BB2_7:
	ret;

}
	// .globl	ThresholdScaleRGBKernel
.visible .entry ThresholdScaleRGBKernel(
	.param .u64 ThresholdScaleRGBKernel_param_0,
	.param .u64 ThresholdScaleRGBKernel_param_1,
	.param .u32 ThresholdScaleRGBKernel_param_2,
	.param .u32 ThresholdScaleRGBKernel_param_3,
	.param .u32 ThresholdScaleRGBKernel_param_4,
	.param .u32 ThresholdScaleRGBKernel_param_5,
	.param .f32 ThresholdScaleRGBKernel_param_6,
	.param .u32 ThresholdScaleRGBKernel_param_7
)
{
	.reg .pred 	%p<7>;
	.reg .b16 	%rs<9>;
	.reg .f32 	%f<42>;
	.reg .b32 	%r<15>;
	.reg .b64 	%rd<14>;


	ld.param.u64 	%rd4, [ThresholdScaleRGBKernel_param_0];
	ld.param.u64 	%rd5, [ThresholdScaleRGBKernel_param_1];
	ld.param.u32 	%r3, [ThresholdScaleRGBKernel_param_2];
	ld.param.u32 	%r4, [ThresholdScaleRGBKernel_param_3];
	ld.param.u32 	%r6, [ThresholdScaleRGBKernel_param_4];
	ld.param.u32 	%r7, [ThresholdScaleRGBKernel_param_5];
	ld.param.f32 	%f22, [ThresholdScaleRGBKernel_param_6];
	ld.param.u32 	%r5, [ThresholdScaleRGBKernel_param_7];
	cvta.to.global.u64 	%rd1, %rd5;
	cvta.to.global.u64 	%rd2, %rd4;
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r10, %tid.x;
	mad.lo.s32 	%r1, %r9, %r8, %r10;
	mov.u32 	%r11, %ntid.y;
	mov.u32 	%r12, %ctaid.y;
	mov.u32 	%r13, %tid.y;
	mad.lo.s32 	%r2, %r12, %r11, %r13;
	setp.ge.s32 	%p1, %r1, %r6;
	setp.ge.s32 	%p2, %r2, %r7;
	or.pred  	%p3, %p1, %p2;
	@%p3 bra 	$L__BB3_9;

	mad.lo.s32 	%r14, %r2, %r3, %r1;
	cvt.s64.s32 	%rd3, %r14;
	setp.eq.s32 	%p4, %r4, 0;
	@%p4 bra 	$L__BB3_3;

	shl.b64 	%rd6, %rd3, 4;
	add.s64 	%rd7, %rd2, %rd6;
	ld.global.v4.f32 	{%f35, %f36, %f37, %f38}, [%rd7];
	bra.uni 	$L__BB3_4;

$L__BB3_3:
	shl.b64 	%rd8, %rd3, 3;
	add.s64 	%rd9, %rd2, %rd8;
	ld.global.u16 	%rs1, [%rd9];
	ld.global.u16 	%rs2, [%rd9+2];
	ld.global.u16 	%rs3, [%rd9+4];
	ld.global.u16 	%rs4, [%rd9+6];
	// begin inline asm
	{  cvt.f32.f16 %f35, %rs1;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f36, %rs2;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f37, %rs3;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f38, %rs4;}

	// end inline asm

$L__BB3_4:
	mul.ftz.f32 	%f39, %f37, %f22;
	mul.ftz.f32 	%f40, %f36, %f22;
	mul.ftz.f32 	%f41, %f35, %f22;
	setp.eq.s32 	%p5, %r5, 0;
	@%p5 bra 	$L__BB3_6;

	cvt.ftz.sat.f32.f32 	%f39, %f39;
	cvt.ftz.sat.f32.f32 	%f40, %f40;
	cvt.ftz.sat.f32.f32 	%f41, %f41;

$L__BB3_6:
	@%p4 bra 	$L__BB3_8;

	shl.b64 	%rd10, %rd3, 4;
	add.s64 	%rd11, %rd1, %rd10;
	st.global.v4.f32 	[%rd11], {%f41, %f40, %f39, %f38};
	bra.uni 	$L__BB3_9;

$L__BB3_8:
	// begin inline asm
	{  cvt.rn.f16.f32 %rs5, %f41;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs6, %f40;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs7, %f39;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs8, %f38;}

	// end inline asm
	shl.b64 	%rd12, %rd3, 3;
	add.s64 	%rd13, %rd1, %rd12;
	st.global.u16 	[%rd13], %rs5;
	st.global.u16 	[%rd13+2], %rs6;
	st.global.u16 	[%rd13+4], %rs7;
	st.global.u16 	[%rd13+6], %rs8;

$L__BB3_9:
	ret;

}
	// .globl	ThresholdArbTableKernel
.visible .entry ThresholdArbTableKernel(
	.param .u64 ThresholdArbTableKernel_param_0,
	.param .u64 ThresholdArbTableKernel_param_1,
	.param .u64 ThresholdArbTableKernel_param_2,
	.param .u64 ThresholdArbTableKernel_param_3,
	.param .u32 ThresholdArbTableKernel_param_4,
	.param .u32 ThresholdArbTableKernel_param_5,
	.param .u32 ThresholdArbTableKernel_param_6,
	.param .u32 ThresholdArbTableKernel_param_7
)
{
	.reg .pred 	%p<6>;
	.reg .b16 	%rs<9>;
	.reg .f32 	%f<41>;
	.reg .b32 	%r<14>;
	.reg .b64 	%rd<16>;


	ld.param.u64 	%rd4, [ThresholdArbTableKernel_param_0];
	ld.param.u64 	%rd5, [ThresholdArbTableKernel_param_3];
	ld.param.u32 	%r3, [ThresholdArbTableKernel_param_4];
	ld.param.u32 	%r4, [ThresholdArbTableKernel_param_5];
	ld.param.u32 	%r5, [ThresholdArbTableKernel_param_6];
	ld.param.u32 	%r6, [ThresholdArbTableKernel_param_7];
	cvta.to.global.u64 	%rd1, %rd5;
	cvta.to.global.u64 	%rd2, %rd4;
	mov.u32 	%r7, %ntid.x;
	mov.u32 	%r8, %ctaid.x;
	mov.u32 	%r9, %tid.x;
	mad.lo.s32 	%r1, %r8, %r7, %r9;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r2, %r11, %r10, %r12;
	setp.ge.s32 	%p1, %r1, %r5;
	setp.ge.s32 	%p2, %r2, %r6;
	or.pred  	%p3, %p1, %p2;
	@%p3 bra 	$L__BB4_7;

	mad.lo.s32 	%r13, %r2, %r3, %r1;
	cvt.s64.s32 	%rd3, %r13;
	setp.eq.s32 	%p4, %r4, 0;
	@%p4 bra 	$L__BB4_3;

	shl.b64 	%rd6, %rd3, 4;
	add.s64 	%rd7, %rd2, %rd6;
	ld.global.f32 	%f40, [%rd7+12];
	bra.uni 	$L__BB4_4;

$L__BB4_3:
	shl.b64 	%rd8, %rd3, 3;
	add.s64 	%rd9, %rd2, %rd8;
	ld.global.u16 	%rs4, [%rd9+6];
	// begin inline asm
	{  cvt.f32.f16 %f40, %rs4;}

	// end inline asm

$L__BB4_4:
	fma.rn.ftz.f32 	%f12, %f40, 0f437F0000, 0f3F000000;
	mov.f32 	%f13, 0f3F000000;
	tex.2d.v4.f32.f32 	{%f14, %f15, %f16, %f17}, [inRGBALUT, {%f12, %f13}];
	mul.ftz.f32 	%f4, %f17, 0f3B808081;
	mul.ftz.f32 	%f18, %f16, 0f3B808081;
	fma.rn.ftz.f32 	%f19, %f18, 0f437F0000, 0f3F000000;
	mul.ftz.f32 	%f20, %f15, 0f3B808081;
	fma.rn.ftz.f32 	%f21, %f20, 0f437F0000, 0f3F000000;
	mul.ftz.f32 	%f22, %f14, 0f3B808081;
	fma.rn.ftz.f32 	%f23, %f22, 0f437F0000, 0f3F000000;
	tex.2d.v4.f32.f32 	{%f24, %f25, %f26, %f27}, [inMLUT, {%f19, %f13}];
	tex.2d.v4.f32.f32 	{%f28, %f29, %f30, %f31}, [inMLUT, {%f21, %f13}];
	tex.2d.v4.f32.f32 	{%f32, %f33, %f34, %f35}, [inMLUT, {%f23, %f13}];
	mul.ftz.f32 	%f5, %f24, 0f3B808081;
	mul.ftz.f32 	%f6, %f28, 0f3B808081;
	mul.ftz.f32 	%f7, %f32, 0f3B808081;
	@%p4 bra 	$L__BB4_6;

	shl.b64 	%rd12, %rd3, 4;
	add.s64 	%rd13, %rd1, %rd12;
	st.global.v4.f32 	[%rd13], {%f7, %f6, %f5, %f4};
	bra.uni 	$L__BB4_7;

$L__BB4_6:
	// begin inline asm
	{  cvt.rn.f16.f32 %rs5, %f7;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs6, %f6;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs7, %f5;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs8, %f4;}

	// end inline asm
	shl.b64 	%rd14, %rd3, 3;
	add.s64 	%rd15, %rd1, %rd14;
	st.global.u16 	[%rd15], %rs5;
	st.global.u16 	[%rd15+2], %rs6;
	st.global.u16 	[%rd15+4], %rs7;
	st.global.u16 	[%rd15+6], %rs8;

$L__BB4_7:
	ret;

}
	// .globl	GlowMultAlphaKernel
.visible .entry GlowMultAlphaKernel(
	.param .u64 GlowMultAlphaKernel_param_0,
	.param .u64 GlowMultAlphaKernel_param_1,
	.param .u64 GlowMultAlphaKernel_param_2,
	.param .u32 GlowMultAlphaKernel_param_3,
	.param .u32 GlowMultAlphaKernel_param_4,
	.param .u32 GlowMultAlphaKernel_param_5,
	.param .u32 GlowMultAlphaKernel_param_6,
	.param .u32 GlowMultAlphaKernel_param_7
)
{
	.reg .pred 	%p<7>;
	.reg .b16 	%rs<13>;
	.reg .f32 	%f<38>;
	.reg .b32 	%r<14>;
	.reg .b64 	%rd<20>;


	ld.param.u64 	%rd5, [GlowMultAlphaKernel_param_0];
	ld.param.u64 	%rd6, [GlowMultAlphaKernel_param_1];
	ld.param.u64 	%rd7, [GlowMultAlphaKernel_param_2];
	ld.param.u32 	%r3, [GlowMultAlphaKernel_param_3];
	ld.param.u32 	%r4, [GlowMultAlphaKernel_param_4];
	ld.param.u32 	%r5, [GlowMultAlphaKernel_param_5];
	ld.param.u32 	%r6, [GlowMultAlphaKernel_param_6];
	cvta.to.global.u64 	%rd1, %rd7;
	cvta.to.global.u64 	%rd2, %rd5;
	cvta.to.global.u64 	%rd3, %rd6;
	mov.u32 	%r7, %ntid.x;
	mov.u32 	%r8, %ctaid.x;
	mov.u32 	%r9, %tid.x;
	mad.lo.s32 	%r1, %r8, %r7, %r9;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r2, %r11, %r10, %r12;
	setp.ge.s32 	%p1, %r1, %r5;
	setp.ge.s32 	%p2, %r2, %r6;
	or.pred  	%p3, %p1, %p2;
	@%p3 bra 	$L__BB5_10;

	mad.lo.s32 	%r13, %r2, %r3, %r1;
	cvt.s64.s32 	%rd4, %r13;
	setp.eq.s32 	%p4, %r4, 0;
	@%p4 bra 	$L__BB5_3;

	shl.b64 	%rd8, %rd4, 4;
	add.s64 	%rd9, %rd3, %rd8;
	ld.global.v4.f32 	{%f33, %f34, %f35, %f36}, [%rd9];
	bra.uni 	$L__BB5_4;

$L__BB5_3:
	shl.b64 	%rd10, %rd4, 3;
	add.s64 	%rd11, %rd3, %rd10;
	ld.global.u16 	%rs1, [%rd11];
	ld.global.u16 	%rs2, [%rd11+2];
	ld.global.u16 	%rs3, [%rd11+4];
	ld.global.u16 	%rs4, [%rd11+6];
	// begin inline asm
	{  cvt.f32.f16 %f33, %rs1;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f34, %rs2;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f35, %rs3;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f36, %rs4;}

	// end inline asm

$L__BB5_4:
	@%p4 bra 	$L__BB5_6;

	shl.b64 	%rd12, %rd4, 4;
	add.s64 	%rd13, %rd2, %rd12;
	ld.global.f32 	%f37, [%rd13+12];
	bra.uni 	$L__BB5_7;

$L__BB5_6:
	shl.b64 	%rd14, %rd4, 3;
	add.s64 	%rd15, %rd2, %rd14;
	ld.global.u16 	%rs8, [%rd15+6];
	// begin inline asm
	{  cvt.f32.f16 %f37, %rs8;}

	// end inline asm

$L__BB5_7:
	mul.ftz.f32 	%f16, %f36, %f37;
	@%p4 bra 	$L__BB5_9;

	shl.b64 	%rd16, %rd4, 4;
	add.s64 	%rd17, %rd1, %rd16;
	st.global.v4.f32 	[%rd17], {%f33, %f34, %f35, %f16};
	bra.uni 	$L__BB5_10;

$L__BB5_9:
	// begin inline asm
	{  cvt.rn.f16.f32 %rs9, %f33;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs10, %f34;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs11, %f35;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs12, %f16;}

	// end inline asm
	shl.b64 	%rd18, %rd4, 3;
	add.s64 	%rd19, %rd1, %rd18;
	st.global.u16 	[%rd19], %rs9;
	st.global.u16 	[%rd19+2], %rs10;
	st.global.u16 	[%rd19+4], %rs11;
	st.global.u16 	[%rd19+6], %rs12;

$L__BB5_10:
	ret;

}
	// .globl	GlowMultAlphaLumaKernel
.visible .entry GlowMultAlphaLumaKernel(
	.param .u64 GlowMultAlphaLumaKernel_param_0,
	.param .u64 GlowMultAlphaLumaKernel_param_1,
	.param .u64 GlowMultAlphaLumaKernel_param_2,
	.param .u32 GlowMultAlphaLumaKernel_param_3,
	.param .u32 GlowMultAlphaLumaKernel_param_4,
	.param .u32 GlowMultAlphaLumaKernel_param_5,
	.param .u32 GlowMultAlphaLumaKernel_param_6,
	.param .u32 GlowMultAlphaLumaKernel_param_7
)
{
	.reg .pred 	%p<9>;
	.reg .b16 	%rs<13>;
	.reg .f32 	%f<66>;
	.reg .b32 	%r<14>;
	.reg .b64 	%rd<20>;


	ld.param.u64 	%rd5, [GlowMultAlphaLumaKernel_param_0];
	ld.param.u64 	%rd6, [GlowMultAlphaLumaKernel_param_1];
	ld.param.u64 	%rd7, [GlowMultAlphaLumaKernel_param_2];
	ld.param.u32 	%r3, [GlowMultAlphaLumaKernel_param_3];
	ld.param.u32 	%r4, [GlowMultAlphaLumaKernel_param_4];
	ld.param.u32 	%r5, [GlowMultAlphaLumaKernel_param_5];
	ld.param.u32 	%r6, [GlowMultAlphaLumaKernel_param_6];
	cvta.to.global.u64 	%rd1, %rd7;
	cvta.to.global.u64 	%rd2, %rd5;
	cvta.to.global.u64 	%rd3, %rd6;
	mov.u32 	%r7, %ntid.x;
	mov.u32 	%r8, %ctaid.x;
	mov.u32 	%r9, %tid.x;
	mad.lo.s32 	%r1, %r8, %r7, %r9;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r2, %r11, %r10, %r12;
	setp.ge.s32 	%p1, %r1, %r5;
	setp.ge.s32 	%p2, %r2, %r6;
	or.pred  	%p3, %p1, %p2;
	@%p3 bra 	$L__BB6_13;

	mad.lo.s32 	%r13, %r2, %r3, %r1;
	cvt.s64.s32 	%rd4, %r13;
	setp.eq.s32 	%p4, %r4, 0;
	@%p4 bra 	$L__BB6_3;

	shl.b64 	%rd8, %rd4, 4;
	add.s64 	%rd9, %rd3, %rd8;
	ld.global.v4.f32 	{%f57, %f58, %f59, %f60}, [%rd9];
	bra.uni 	$L__BB6_4;

$L__BB6_3:
	shl.b64 	%rd10, %rd4, 3;
	add.s64 	%rd11, %rd3, %rd10;
	ld.global.u16 	%rs1, [%rd11];
	ld.global.u16 	%rs2, [%rd11+2];
	ld.global.u16 	%rs3, [%rd11+4];
	ld.global.u16 	%rs4, [%rd11+6];
	// begin inline asm
	{  cvt.f32.f16 %f57, %rs1;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f58, %rs2;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f59, %rs3;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f60, %rs4;}

	// end inline asm

$L__BB6_4:
	@%p4 bra 	$L__BB6_6;

	shl.b64 	%rd12, %rd4, 4;
	add.s64 	%rd13, %rd2, %rd12;
	ld.global.v4.f32 	{%f61, %f62, %f63, %f64}, [%rd13];
	bra.uni 	$L__BB6_7;

$L__BB6_6:
	shl.b64 	%rd14, %rd4, 3;
	add.s64 	%rd15, %rd2, %rd14;
	ld.global.u16 	%rs5, [%rd15];
	ld.global.u16 	%rs6, [%rd15+2];
	ld.global.u16 	%rs7, [%rd15+4];
	ld.global.u16 	%rs8, [%rd15+6];
	// begin inline asm
	{  cvt.f32.f16 %f61, %rs5;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f62, %rs6;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f63, %rs7;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f64, %rs8;}

	// end inline asm

$L__BB6_7:
	ld.const.f32 	%f44, [kRGB32f_To_601YPbPr];
	ld.const.f32 	%f45, [kRGB32f_To_601YPbPr+4];
	mul.ftz.f32 	%f46, %f62, %f45;
	fma.rn.ftz.f32 	%f47, %f63, %f44, %f46;
	ld.const.f32 	%f48, [kRGB32f_To_601YPbPr+8];
	fma.rn.ftz.f32 	%f49, %f61, %f48, %f47;
	mul.ftz.f32 	%f50, %f60, %f49;
	mul.ftz.f32 	%f25, %f64, %f50;
	setp.gt.ftz.f32 	%p6, %f25, 0f3F800000;
	mov.f32 	%f65, 0f3F800000;
	@%p6 bra 	$L__BB6_10;

	ld.const.f32 	%f51, [kMinAlphaValue];
	setp.geu.ftz.f32 	%p7, %f25, %f51;
	mov.f32 	%f65, %f25;
	@%p7 bra 	$L__BB6_10;

	mov.f32 	%f65, 0f00000000;

$L__BB6_10:
	@%p4 bra 	$L__BB6_12;

	shl.b64 	%rd16, %rd4, 4;
	add.s64 	%rd17, %rd1, %rd16;
	st.global.v4.f32 	[%rd17], {%f57, %f58, %f59, %f65};
	bra.uni 	$L__BB6_13;

$L__BB6_12:
	// begin inline asm
	{  cvt.rn.f16.f32 %rs9, %f57;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs10, %f58;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs11, %f59;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs12, %f65;}

	// end inline asm
	shl.b64 	%rd18, %rd4, 3;
	add.s64 	%rd19, %rd1, %rd18;
	st.global.u16 	[%rd19], %rs9;
	st.global.u16 	[%rd19+2], %rs10;
	st.global.u16 	[%rd19+4], %rs11;
	st.global.u16 	[%rd19+6], %rs12;

$L__BB6_13:
	ret;

}
	// .globl	GlowMultNotAlphaKernel
.visible .entry GlowMultNotAlphaKernel(
	.param .u64 GlowMultNotAlphaKernel_param_0,
	.param .u64 GlowMultNotAlphaKernel_param_1,
	.param .u64 GlowMultNotAlphaKernel_param_2,
	.param .u32 GlowMultNotAlphaKernel_param_3,
	.param .u32 GlowMultNotAlphaKernel_param_4,
	.param .u32 GlowMultNotAlphaKernel_param_5,
	.param .u32 GlowMultNotAlphaKernel_param_6,
	.param .u32 GlowMultNotAlphaKernel_param_7
)
{
	.reg .pred 	%p<7>;
	.reg .b16 	%rs<13>;
	.reg .f32 	%f<40>;
	.reg .b32 	%r<14>;
	.reg .b64 	%rd<20>;


	ld.param.u64 	%rd5, [GlowMultNotAlphaKernel_param_0];
	ld.param.u64 	%rd6, [GlowMultNotAlphaKernel_param_1];
	ld.param.u64 	%rd7, [GlowMultNotAlphaKernel_param_2];
	ld.param.u32 	%r3, [GlowMultNotAlphaKernel_param_3];
	ld.param.u32 	%r4, [GlowMultNotAlphaKernel_param_4];
	ld.param.u32 	%r5, [GlowMultNotAlphaKernel_param_5];
	ld.param.u32 	%r6, [GlowMultNotAlphaKernel_param_6];
	cvta.to.global.u64 	%rd1, %rd7;
	cvta.to.global.u64 	%rd2, %rd5;
	cvta.to.global.u64 	%rd3, %rd6;
	mov.u32 	%r7, %ntid.x;
	mov.u32 	%r8, %ctaid.x;
	mov.u32 	%r9, %tid.x;
	mad.lo.s32 	%r1, %r8, %r7, %r9;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r2, %r11, %r10, %r12;
	setp.ge.s32 	%p1, %r1, %r5;
	setp.ge.s32 	%p2, %r2, %r6;
	or.pred  	%p3, %p1, %p2;
	@%p3 bra 	$L__BB7_10;

	mad.lo.s32 	%r13, %r2, %r3, %r1;
	cvt.s64.s32 	%rd4, %r13;
	setp.eq.s32 	%p4, %r4, 0;
	@%p4 bra 	$L__BB7_3;

	shl.b64 	%rd8, %rd4, 4;
	add.s64 	%rd9, %rd3, %rd8;
	ld.global.v4.f32 	{%f35, %f36, %f37, %f38}, [%rd9];
	bra.uni 	$L__BB7_4;

$L__BB7_3:
	shl.b64 	%rd10, %rd4, 3;
	add.s64 	%rd11, %rd3, %rd10;
	ld.global.u16 	%rs1, [%rd11];
	ld.global.u16 	%rs2, [%rd11+2];
	ld.global.u16 	%rs3, [%rd11+4];
	ld.global.u16 	%rs4, [%rd11+6];
	// begin inline asm
	{  cvt.f32.f16 %f35, %rs1;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f36, %rs2;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f37, %rs3;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f38, %rs4;}

	// end inline asm

$L__BB7_4:
	@%p4 bra 	$L__BB7_6;

	shl.b64 	%rd12, %rd4, 4;
	add.s64 	%rd13, %rd2, %rd12;
	ld.global.f32 	%f39, [%rd13+12];
	bra.uni 	$L__BB7_7;

$L__BB7_6:
	shl.b64 	%rd14, %rd4, 3;
	add.s64 	%rd15, %rd2, %rd14;
	ld.global.u16 	%rs8, [%rd15+6];
	// begin inline asm
	{  cvt.f32.f16 %f39, %rs8;}

	// end inline asm

$L__BB7_7:
	mov.f32 	%f29, 0f3F800000;
	sub.ftz.f32 	%f30, %f29, %f39;
	mul.ftz.f32 	%f16, %f38, %f30;
	@%p4 bra 	$L__BB7_9;

	shl.b64 	%rd16, %rd4, 4;
	add.s64 	%rd17, %rd1, %rd16;
	st.global.v4.f32 	[%rd17], {%f35, %f36, %f37, %f16};
	bra.uni 	$L__BB7_10;

$L__BB7_9:
	// begin inline asm
	{  cvt.rn.f16.f32 %rs9, %f35;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs10, %f36;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs11, %f37;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs12, %f16;}

	// end inline asm
	shl.b64 	%rd18, %rd4, 3;
	add.s64 	%rd19, %rd1, %rd18;
	st.global.u16 	[%rd19], %rs9;
	st.global.u16 	[%rd19+2], %rs10;
	st.global.u16 	[%rd19+4], %rs11;
	st.global.u16 	[%rd19+6], %rs12;

$L__BB7_10:
	ret;

}
	// .globl	GlowMultNotAlphaLumaKernel
.visible .entry GlowMultNotAlphaLumaKernel(
	.param .u64 GlowMultNotAlphaLumaKernel_param_0,
	.param .u64 GlowMultNotAlphaLumaKernel_param_1,
	.param .u64 GlowMultNotAlphaLumaKernel_param_2,
	.param .u32 GlowMultNotAlphaLumaKernel_param_3,
	.param .u32 GlowMultNotAlphaLumaKernel_param_4,
	.param .u32 GlowMultNotAlphaLumaKernel_param_5,
	.param .u32 GlowMultNotAlphaLumaKernel_param_6,
	.param .u32 GlowMultNotAlphaLumaKernel_param_7
)
{
	.reg .pred 	%p<9>;
	.reg .b16 	%rs<13>;
	.reg .f32 	%f<67>;
	.reg .b32 	%r<14>;
	.reg .b64 	%rd<20>;


	ld.param.u64 	%rd5, [GlowMultNotAlphaLumaKernel_param_0];
	ld.param.u64 	%rd6, [GlowMultNotAlphaLumaKernel_param_1];
	ld.param.u64 	%rd7, [GlowMultNotAlphaLumaKernel_param_2];
	ld.param.u32 	%r3, [GlowMultNotAlphaLumaKernel_param_3];
	ld.param.u32 	%r4, [GlowMultNotAlphaLumaKernel_param_4];
	ld.param.u32 	%r5, [GlowMultNotAlphaLumaKernel_param_5];
	ld.param.u32 	%r6, [GlowMultNotAlphaLumaKernel_param_6];
	cvta.to.global.u64 	%rd1, %rd7;
	cvta.to.global.u64 	%rd2, %rd5;
	cvta.to.global.u64 	%rd3, %rd6;
	mov.u32 	%r7, %ntid.x;
	mov.u32 	%r8, %ctaid.x;
	mov.u32 	%r9, %tid.x;
	mad.lo.s32 	%r1, %r8, %r7, %r9;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r2, %r11, %r10, %r12;
	setp.ge.s32 	%p1, %r1, %r5;
	setp.ge.s32 	%p2, %r2, %r6;
	or.pred  	%p3, %p1, %p2;
	@%p3 bra 	$L__BB8_13;

	mad.lo.s32 	%r13, %r2, %r3, %r1;
	cvt.s64.s32 	%rd4, %r13;
	setp.eq.s32 	%p4, %r4, 0;
	@%p4 bra 	$L__BB8_3;

	shl.b64 	%rd8, %rd4, 4;
	add.s64 	%rd9, %rd3, %rd8;
	ld.global.v4.f32 	{%f58, %f59, %f60, %f61}, [%rd9];
	bra.uni 	$L__BB8_4;

$L__BB8_3:
	shl.b64 	%rd10, %rd4, 3;
	add.s64 	%rd11, %rd3, %rd10;
	ld.global.u16 	%rs1, [%rd11];
	ld.global.u16 	%rs2, [%rd11+2];
	ld.global.u16 	%rs3, [%rd11+4];
	ld.global.u16 	%rs4, [%rd11+6];
	// begin inline asm
	{  cvt.f32.f16 %f58, %rs1;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f59, %rs2;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f60, %rs3;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f61, %rs4;}

	// end inline asm

$L__BB8_4:
	@%p4 bra 	$L__BB8_6;

	shl.b64 	%rd12, %rd4, 4;
	add.s64 	%rd13, %rd2, %rd12;
	ld.global.v4.f32 	{%f62, %f63, %f64, %f65}, [%rd13];
	bra.uni 	$L__BB8_7;

$L__BB8_6:
	shl.b64 	%rd14, %rd4, 3;
	add.s64 	%rd15, %rd2, %rd14;
	ld.global.u16 	%rs5, [%rd15];
	ld.global.u16 	%rs6, [%rd15+2];
	ld.global.u16 	%rs7, [%rd15+4];
	ld.global.u16 	%rs8, [%rd15+6];
	// begin inline asm
	{  cvt.f32.f16 %f62, %rs5;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f63, %rs6;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f64, %rs7;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f65, %rs8;}

	// end inline asm

$L__BB8_7:
	ld.const.f32 	%f44, [kRGB32f_To_601YPbPr];
	ld.const.f32 	%f45, [kRGB32f_To_601YPbPr+4];
	mul.ftz.f32 	%f46, %f63, %f45;
	fma.rn.ftz.f32 	%f47, %f64, %f44, %f46;
	ld.const.f32 	%f48, [kRGB32f_To_601YPbPr+8];
	fma.rn.ftz.f32 	%f49, %f62, %f48, %f47;
	mul.ftz.f32 	%f50, %f65, %f49;
	mov.f32 	%f66, 0f3F800000;
	sub.ftz.f32 	%f51, %f66, %f50;
	mul.ftz.f32 	%f25, %f61, %f51;
	setp.gt.ftz.f32 	%p6, %f25, 0f3F800000;
	@%p6 bra 	$L__BB8_10;

	ld.const.f32 	%f52, [kMinAlphaValue];
	setp.geu.ftz.f32 	%p7, %f25, %f52;
	mov.f32 	%f66, %f25;
	@%p7 bra 	$L__BB8_10;

	mov.f32 	%f66, 0f00000000;

$L__BB8_10:
	@%p4 bra 	$L__BB8_12;

	shl.b64 	%rd16, %rd4, 4;
	add.s64 	%rd17, %rd1, %rd16;
	st.global.v4.f32 	[%rd17], {%f58, %f59, %f60, %f66};
	bra.uni 	$L__BB8_13;

$L__BB8_12:
	// begin inline asm
	{  cvt.rn.f16.f32 %rs9, %f58;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs10, %f59;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs11, %f60;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs12, %f66;}

	// end inline asm
	shl.b64 	%rd18, %rd4, 3;
	add.s64 	%rd19, %rd1, %rd18;
	st.global.u16 	[%rd19], %rs9;
	st.global.u16 	[%rd19+2], %rs10;
	st.global.u16 	[%rd19+4], %rs11;
	st.global.u16 	[%rd19+6], %rs12;

$L__BB8_13:
	ret;

}
	// .globl	GlowAdditivePremulKernel
.visible .entry GlowAdditivePremulKernel(
	.param .u64 GlowAdditivePremulKernel_param_0,
	.param .u64 GlowAdditivePremulKernel_param_1,
	.param .u64 GlowAdditivePremulKernel_param_2,
	.param .u32 GlowAdditivePremulKernel_param_3,
	.param .u32 GlowAdditivePremulKernel_param_4,
	.param .u32 GlowAdditivePremulKernel_param_5,
	.param .u32 GlowAdditivePremulKernel_param_6,
	.param .u32 GlowAdditivePremulKernel_param_7
)
{
	.reg .pred 	%p<9>;
	.reg .b16 	%rs<13>;
	.reg .f32 	%f<83>;
	.reg .b32 	%r<15>;
	.reg .b64 	%rd<20>;


	ld.param.u64 	%rd5, [GlowAdditivePremulKernel_param_0];
	ld.param.u64 	%rd6, [GlowAdditivePremulKernel_param_1];
	ld.param.u64 	%rd7, [GlowAdditivePremulKernel_param_2];
	ld.param.u32 	%r3, [GlowAdditivePremulKernel_param_3];
	ld.param.u32 	%r4, [GlowAdditivePremulKernel_param_4];
	ld.param.u32 	%r6, [GlowAdditivePremulKernel_param_5];
	ld.param.u32 	%r7, [GlowAdditivePremulKernel_param_6];
	ld.param.u32 	%r5, [GlowAdditivePremulKernel_param_7];
	cvta.to.global.u64 	%rd1, %rd7;
	cvta.to.global.u64 	%rd2, %rd5;
	cvta.to.global.u64 	%rd3, %rd6;
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r10, %tid.x;
	mad.lo.s32 	%r1, %r9, %r8, %r10;
	mov.u32 	%r11, %ntid.y;
	mov.u32 	%r12, %ctaid.y;
	mov.u32 	%r13, %tid.y;
	mad.lo.s32 	%r2, %r12, %r11, %r13;
	setp.ge.s32 	%p1, %r1, %r6;
	setp.ge.s32 	%p2, %r2, %r7;
	or.pred  	%p3, %p1, %p2;
	@%p3 bra 	$L__BB9_14;

	mad.lo.s32 	%r14, %r2, %r3, %r1;
	cvt.s64.s32 	%rd4, %r14;
	setp.eq.s32 	%p4, %r4, 0;
	@%p4 bra 	$L__BB9_3;

	shl.b64 	%rd8, %rd4, 4;
	add.s64 	%rd9, %rd3, %rd8;
	ld.global.v4.f32 	{%f79, %f78, %f77, %f76}, [%rd9];
	bra.uni 	$L__BB9_4;

$L__BB9_3:
	shl.b64 	%rd10, %rd4, 3;
	add.s64 	%rd11, %rd3, %rd10;
	ld.global.u16 	%rs1, [%rd11];
	ld.global.u16 	%rs2, [%rd11+2];
	ld.global.u16 	%rs3, [%rd11+4];
	ld.global.u16 	%rs4, [%rd11+6];
	// begin inline asm
	{  cvt.f32.f16 %f79, %rs1;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f78, %rs2;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f77, %rs3;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f76, %rs4;}

	// end inline asm

$L__BB9_4:
	@%p4 bra 	$L__BB9_6;

	shl.b64 	%rd12, %rd4, 4;
	add.s64 	%rd13, %rd2, %rd12;
	ld.global.v4.f32 	{%f72, %f73, %f74, %f75}, [%rd13];
	bra.uni 	$L__BB9_7;

$L__BB9_6:
	shl.b64 	%rd14, %rd4, 3;
	add.s64 	%rd15, %rd2, %rd14;
	ld.global.u16 	%rs5, [%rd15];
	ld.global.u16 	%rs6, [%rd15+2];
	ld.global.u16 	%rs7, [%rd15+4];
	ld.global.u16 	%rs8, [%rd15+6];
	// begin inline asm
	{  cvt.f32.f16 %f72, %rs5;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f73, %rs6;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f74, %rs7;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f75, %rs8;}

	// end inline asm

$L__BB9_7:
	mov.f32 	%f56, 0f3F800000;
	sub.ftz.f32 	%f57, %f56, %f75;
	mul.ftz.f32 	%f25, %f76, %f57;
	sub.ftz.f32 	%f58, %f56, %f76;
	mul.ftz.f32 	%f59, %f58, %f57;
	sub.ftz.f32 	%f26, %f56, %f59;
	ld.const.f32 	%f60, [kMinAlphaValue];
	setp.leu.ftz.f32 	%p6, %f26, %f60;
	@%p6 bra 	$L__BB9_9;

	fma.rn.ftz.f32 	%f61, %f77, %f25, %f74;
	div.approx.ftz.f32 	%f77, %f61, %f26;
	fma.rn.ftz.f32 	%f62, %f78, %f25, %f73;
	div.approx.ftz.f32 	%f78, %f62, %f26;
	fma.rn.ftz.f32 	%f63, %f79, %f25, %f72;
	div.approx.ftz.f32 	%f79, %f63, %f26;
	mov.f32 	%f76, %f26;

$L__BB9_9:
	setp.eq.s32 	%p7, %r5, 0;
	@%p7 bra 	$L__BB9_11;

	cvt.ftz.sat.f32.f32 	%f77, %f77;
	cvt.ftz.sat.f32.f32 	%f78, %f78;
	cvt.ftz.sat.f32.f32 	%f79, %f79;

$L__BB9_11:
	@%p4 bra 	$L__BB9_13;

	shl.b64 	%rd16, %rd4, 4;
	add.s64 	%rd17, %rd1, %rd16;
	st.global.v4.f32 	[%rd17], {%f79, %f78, %f77, %f76};
	bra.uni 	$L__BB9_14;

$L__BB9_13:
	// begin inline asm
	{  cvt.rn.f16.f32 %rs9, %f79;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs10, %f78;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs11, %f77;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs12, %f76;}

	// end inline asm
	shl.b64 	%rd18, %rd4, 3;
	add.s64 	%rd19, %rd1, %rd18;
	st.global.u16 	[%rd19], %rs9;
	st.global.u16 	[%rd19+2], %rs10;
	st.global.u16 	[%rd19+4], %rs11;
	st.global.u16 	[%rd19+6], %rs12;

$L__BB9_14:
	ret;

}
	// .globl	GlowAlphaAddKernel
.visible .entry GlowAlphaAddKernel(
	.param .u64 GlowAlphaAddKernel_param_0,
	.param .u64 GlowAlphaAddKernel_param_1,
	.param .u64 GlowAlphaAddKernel_param_2,
	.param .u32 GlowAlphaAddKernel_param_3,
	.param .u32 GlowAlphaAddKernel_param_4,
	.param .u32 GlowAlphaAddKernel_param_5,
	.param .u32 GlowAlphaAddKernel_param_6,
	.param .u32 GlowAlphaAddKernel_param_7
)
{
	.reg .pred 	%p<10>;
	.reg .b16 	%rs<13>;
	.reg .f32 	%f<81>;
	.reg .b32 	%r<14>;
	.reg .b64 	%rd<20>;


	ld.param.u64 	%rd5, [GlowAlphaAddKernel_param_0];
	ld.param.u64 	%rd6, [GlowAlphaAddKernel_param_1];
	ld.param.u64 	%rd7, [GlowAlphaAddKernel_param_2];
	ld.param.u32 	%r3, [GlowAlphaAddKernel_param_3];
	ld.param.u32 	%r4, [GlowAlphaAddKernel_param_4];
	ld.param.u32 	%r5, [GlowAlphaAddKernel_param_5];
	ld.param.u32 	%r6, [GlowAlphaAddKernel_param_6];
	cvta.to.global.u64 	%rd1, %rd7;
	cvta.to.global.u64 	%rd2, %rd5;
	cvta.to.global.u64 	%rd3, %rd6;
	mov.u32 	%r7, %ntid.x;
	mov.u32 	%r8, %ctaid.x;
	mov.u32 	%r9, %tid.x;
	mad.lo.s32 	%r1, %r8, %r7, %r9;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r2, %r11, %r10, %r12;
	setp.ge.s32 	%p1, %r1, %r5;
	setp.ge.s32 	%p2, %r2, %r6;
	or.pred  	%p3, %p1, %p2;
	@%p3 bra 	$L__BB10_15;

	mad.lo.s32 	%r13, %r2, %r3, %r1;
	cvt.s64.s32 	%rd4, %r13;
	setp.eq.s32 	%p4, %r4, 0;
	@%p4 bra 	$L__BB10_3;

	shl.b64 	%rd8, %rd4, 4;
	add.s64 	%rd9, %rd3, %rd8;
	ld.global.v4.f32 	{%f69, %f70, %f71, %f72}, [%rd9];
	bra.uni 	$L__BB10_4;

$L__BB10_3:
	shl.b64 	%rd10, %rd4, 3;
	add.s64 	%rd11, %rd3, %rd10;
	ld.global.u16 	%rs1, [%rd11];
	ld.global.u16 	%rs2, [%rd11+2];
	ld.global.u16 	%rs3, [%rd11+4];
	ld.global.u16 	%rs4, [%rd11+6];
	// begin inline asm
	{  cvt.f32.f16 %f69, %rs1;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f70, %rs2;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f71, %rs3;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f72, %rs4;}

	// end inline asm

$L__BB10_4:
	@%p4 bra 	$L__BB10_6;

	shl.b64 	%rd12, %rd4, 4;
	add.s64 	%rd13, %rd2, %rd12;
	ld.global.v4.f32 	{%f73, %f74, %f75, %f76}, [%rd13];
	bra.uni 	$L__BB10_7;

$L__BB10_6:
	shl.b64 	%rd14, %rd4, 3;
	add.s64 	%rd15, %rd2, %rd14;
	ld.global.u16 	%rs5, [%rd15];
	ld.global.u16 	%rs6, [%rd15+2];
	ld.global.u16 	%rs7, [%rd15+4];
	ld.global.u16 	%rs8, [%rd15+6];
	// begin inline asm
	{  cvt.f32.f16 %f73, %rs5;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f74, %rs6;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f75, %rs7;}

	// end inline asm
	// begin inline asm
	{  cvt.f32.f16 %f76, %rs8;}

	// end inline asm

$L__BB10_7:
	add.ftz.f32 	%f25, %f72, %f76;
	setp.eq.ftz.f32 	%p6, %f76, 0f3F800000;
	mov.f32 	%f77, 0f3F800000;
	mov.f32 	%f78, %f75;
	mov.f32 	%f79, %f74;
	mov.f32 	%f80, %f73;
	@%p6 bra 	$L__BB10_12;

	setp.ltu.ftz.f32 	%p7, %f25, 0f3F800000;
	@%p7 bra 	$L__BB10_10;
	bra.uni 	$L__BB10_9;

$L__BB10_10:
	ld.const.f32 	%f58, [kMinAlphaValue];
	setp.leu.ftz.f32 	%p8, %f25, %f58;
	mov.f32 	%f77, %f72;
	mov.f32 	%f78, %f71;
	mov.f32 	%f79, %f70;
	mov.f32 	%f80, %f69;
	@%p8 bra 	$L__BB10_12;

	mul.ftz.f32 	%f59, %f75, %f76;
	fma.rn.ftz.f32 	%f60, %f71, %f72, %f59;
	div.approx.ftz.f32 	%f78, %f60, %f25;
	mul.ftz.f32 	%f61, %f74, %f76;
	fma.rn.ftz.f32 	%f62, %f70, %f72, %f61;
	div.approx.ftz.f32 	%f79, %f62, %f25;
	mul.ftz.f32 	%f63, %f73, %f76;
	fma.rn.ftz.f32 	%f64, %f69, %f72, %f63;
	div.approx.ftz.f32 	%f80, %f64, %f25;
	mov.f32 	%f77, %f25;
	bra.uni 	$L__BB10_12;

$L__BB10_9:
	mov.f32 	%f77, 0f3F800000;
	sub.ftz.f32 	%f54, %f77, %f76;
	mul.ftz.f32 	%f55, %f71, %f54;
	fma.rn.ftz.f32 	%f78, %f75, %f76, %f55;
	mul.ftz.f32 	%f56, %f70, %f54;
	fma.rn.ftz.f32 	%f79, %f74, %f76, %f56;
	mul.ftz.f32 	%f57, %f69, %f54;
	fma.rn.ftz.f32 	%f80, %f73, %f76, %f57;

$L__BB10_12:
	@%p4 bra 	$L__BB10_14;

	shl.b64 	%rd16, %rd4, 4;
	add.s64 	%rd17, %rd1, %rd16;
	st.global.v4.f32 	[%rd17], {%f80, %f79, %f78, %f77};
	bra.uni 	$L__BB10_15;

$L__BB10_14:
	// begin inline asm
	{  cvt.rn.f16.f32 %rs9, %f80;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs10, %f79;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs11, %f78;}

	// end inline asm
	// begin inline asm
	{  cvt.rn.f16.f32 %rs12, %f77;}

	// end inline asm
	shl.b64 	%rd18, %rd4, 3;
	add.s64 	%rd19, %rd1, %rd18;
	st.global.u16 	[%rd19], %rs9;
	st.global.u16 	[%rd19+2], %rs10;
	st.global.u16 	[%rd19+4], %rs11;
	st.global.u16 	[%rd19+6], %rs12;

$L__BB10_15:
	ret;

}

  ELF3         {           @|      q      V2 @ 8  @ +   .shstrtab .strtab .symtab .symtab_shndx .nv.uft.entry .nv.info .text.GlowAlphaAddKernel .nv.info.GlowAlphaAddKernel .nv.shared.GlowAlphaAddKernel .nv.constant3 .nv.constant0.GlowAlphaAddKernel .text.GlowAdditivePremulKernel .nv.info.GlowAdditivePremulKernel .nv.shared.GlowAdditivePremulKernel .nv.constant0.GlowAdditivePremulKernel .text.GlowMultNotAlphaLumaKernel .nv.info.GlowMultNotAlphaLumaKernel .nv.shared.GlowMultNotAlphaLumaKernel .nv.constant0.GlowMultNotAlphaLumaKernel .text.GlowMultNotAlphaKernel .nv.info.GlowMultNotAlphaKernel .nv.shared.GlowMultNotAlphaKernel .nv.constant0.GlowMultNotAlphaKernel .text.GlowMultAlphaLumaKernel .nv.info.GlowMultAlphaLumaKernel .nv.shared.GlowMultAlphaLumaKernel .nv.constant0.GlowMultAlphaLumaKernel .text.GlowMultAlphaKernel .nv.info.GlowMultAlphaKernel .nv.shared.GlowMultAlphaKernel .nv.constant0.GlowMultAlphaKernel .text.ThresholdArbTableKernel .nv.info.ThresholdArbTableKernel .nv.shared.ThresholdArbTableKernel .nv.constant0.ThresholdArbTableKernel .text.ThresholdScaleRGBKernel .nv.info.ThresholdScaleRGBKernel .nv.shared.ThresholdScaleRGBKernel .nv.constant0.ThresholdScaleRGBKernel .text.ThresholdLookupLuminanceKernel .nv.info.ThresholdLookupLuminanceKernel .nv.shared.ThresholdLookupLuminanceKernel .nv.constant0.ThresholdLookupLuminanceKernel .text.ThresholdLookupRGBKernel .nv.info.ThresholdLookupRGBKernel .nv.shared.ThresholdLookupRGBKernel .nv.constant0.ThresholdLookupRGBKernel .text.ThresholdLookupAlphaKernel .nv.info.ThresholdLookupAlphaKernel .nv.shared.ThresholdLookupAlphaKernel .nv.constant0.ThresholdLookupAlphaKernel .debug_frame .rel.debug_frame .rela.debug_frame .rel.nv.constant0.ThresholdArbTableKernel .nv.rel.action  .shstrtab .strtab .symtab .symtab_shndx .nv.uft.entry .nv.info GlowAlphaAddKernel .text.GlowAlphaAddKernel .nv.info.GlowAlphaAddKernel .nv.shared.GlowAlphaAddKernel .nv.constant3 kRGB32f_To_601YPbPr k601YPbPr_To_RGB32f kRGB32f_To_601YCbCr k601YCbCr_To_RGB32f kRGB8u_To_601YCbCr k601YCbCr_To_RGB8u kRGB8u_To_601YCbCrFullRange k601YCbCrFullRange_To_RGB8u kRGB32f_To_601YCbCrFullRange k601YCbCrFullRange_To_RGB32f kRGB32f_To_709YPbPr k709YPbPr_To_RGB32f kRGB32f_To_709YCbCr k709YCbCr_To_RGB32f k709YCbCrFullRange_To_RGB32f kRGB8u_To_709YCbCr k709YCbCr_To_RGB8u k709YCbCr_To_601YCbCr k601YCbCr_To_709YCbCr kZeroMatrix kYCbCrOffset kYCbCrFullRangeOffset PQ_m1 PQ_m1Inv PQ_m2 PQ_m2Inv PQ_c1 PQ_c2 PQ_c3 Gamma1886 PQ_Lpeak PQ_a PQ_b PQ_c PQ_s PQ_g scaleFD HLG_a HLG_b HLG_c HLG_inva HLG_alpha HLG_invAlpha HLG_gamma HLG_gammaM1 HLG_gammaM1Dgamma HLG_YR HLG_YG HLG_YB HLG_Lpeak inRGBALUT inMLUT kMinAlphaValue .nv.constant0.GlowAlphaAddKernel _param GlowAdditivePremulKernel .text.GlowAdditivePremulKernel .nv.info.GlowAdditivePremulKernel .nv.shared.GlowAdditivePremulKernel .nv.constant0.GlowAdditivePremulKernel GlowMultNotAlphaLumaKernel .text.GlowMultNotAlphaLumaKernel .nv.info.GlowMultNotAlphaLumaKernel .nv.shared.GlowMultNotAlphaLumaKernel .nv.constant0.GlowMultNotAlphaLumaKernel GlowMultNotAlphaKernel .text.GlowMultNotAlphaKernel .nv.info.GlowMultNotAlphaKernel .nv.shared.GlowMultNotAlphaKernel .nv.constant0.GlowMultNotAlphaKernel GlowMultAlphaLumaKernel .text.GlowMultAlphaLumaKernel .nv.info.GlowMultAlphaLumaKernel .nv.shared.GlowMultAlphaLumaKernel .nv.constant0.GlowMultAlphaLumaKernel GlowMultAlphaKernel .text.GlowMultAlphaKernel .nv.info.GlowMultAlphaKernel .nv.shared.GlowMultAlphaKernel .nv.constant0.GlowMultAlphaKernel ThresholdArbTableKernel .text.ThresholdArbTableKernel .nv.info.ThresholdArbTableKernel .nv.shared.ThresholdArbTableKernel .nv.constant0.ThresholdArbTableKernel $BINDLESS$ThresholdArbTableKernel$inRGBALUT $BINDLESS$ThresholdArbTableKernel$inMLUT ThresholdScaleRGBKernel .text.ThresholdScaleRGBKernel .nv.info.ThresholdScaleRGBKernel .nv.shared.ThresholdScaleRGBKernel .nv.constant0.ThresholdScaleRGBKernel ThresholdLookupLuminanceKernel .text.ThresholdLookupLuminanceKernel .nv.info.ThresholdLookupLuminanceKernel .nv.shared.ThresholdLookupLuminanceKernel .nv.constant0.ThresholdLookupLuminanceKernel ThresholdLookupRGBKernel .text.ThresholdLookupRGBKernel .nv.info.ThresholdLookupRGBKernel .nv.shared.ThresholdLookupRGBKernel .nv.constant0.ThresholdLookupRGBKernel ThresholdLookupAlphaKernel .text.ThresholdLookupAlphaKernel .nv.info.ThresholdLookupAlphaKernel .nv.shared.ThresholdLookupAlphaKernel .nv.constant0.ThresholdLookupAlphaKernel .debug_frame .rel.debug_frame .rela.debug_frame .rel.nv.constant0.ThresholdArbTableKernel .nv.rel.action                               S                                                        $            $       $            H       $            l       $                  $                  $       *           $       F           $       b           $           D      $           h      $                 $                 $                 $                 $       	          $           @      $       /    d      $       E          $       [          $       g                 t                                                                                                                                                                                                                                                                                      $                 (                 ,                  0             	    4                 8                  <             *    @             6    D             H    H             O    L             V    P             ]    T             x    X                                    !                 -                    o   "                                        #                 y                       $                                     R   %                                        &                 D                       '                 9                    ~   (                                     ;	   )                 	                    	   *                 M
                    v
                    
                    @                   g                     q                       !               T  "                  #                  $                >  %                  &                 '                _  (               "	  )               	  *               $        |( ((   4                                $   ( <         $        |( ((   4       p                        $   (           $        |( ((   4                                $   (           $        |( ((   4       P                        $   (           $        |( ((   4                               $   (           $        |( ((   4       0                        $   (           $        |( ((   4                              $   (           $        |( ((   4                               $   (           $        |( ((   4                              $   (           $        |( ((   4                              $   (           $        |( ((   4       `                       $   (           / Y      # Y        Y        Y       / X      # X        X        X       / W      # W        W        W       / V      # V        V        V       / U      # U        U        U       / T      # T        T        T       / S      # S        S        S       / R      # R        R        R       / Q      # Q        Q        Q       / P      # P        P        P       / M      # M        M        M       7 {   5  
 6   `, ,       (         $                                       !         !           !               7 {   5  
 8   `, ,       (         $                                       !         !           !        p  7 {   5  
 :   `, ,       (         $                                       !         !           !        P       7 {   5  
 <   `, ,       (         $                                       !         !           !        @  7 {   5  
 >   `, ,       (         $                                       !         !           !        P       7 {   5  
 @   `, ,       (         $                                       !         !           !        0  7 {   5  
 B   `0 0       ,         (         $                     !         !         !           !            7 {   5  
 D   `( (       $                                                         !           !      `    7 {   5  
 F   `0 0      	 ,         (         $                                                         !           !        p  7 {   5  
 H   `0 0      	 ,         (         $                                                         !           !          7 {   5  
 J   `0 0      	 ,         (         $                                                         !           !               s          % 6         Y   4         X            W   T         V            U   t         T            S            R   $         Q             P   D          M            O            N   >E?x=!,o   ?   ?F^־膦  ?    t?  ?26  ??    FB C^A!0g  B  BoF%;    ;%;(ɺP%;<    y>?=>>NG
?    J?
?ȾP
?N@    >E?x=,'>>+վ;ߥ  ?    H?  ?6  ??    q}B\C\Ao+1H  B  BX9;    t;;26;;    гY>Y7?ݓ=Vž   ?   ?;  ?    ?  ??  ?M?    j<:BC|AO  B  BuQ$%;    ^;%;!9[%;R<    ;    ;;=?ﺃ;R;    :>5>?}=νY>>B̾$
?    x?
?5^Zl
?1@      ?d=MD>    g}?
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     y      &   ( y      "   ( y       %   h y      !   b $z     z  a  pb  $z       / z   `  pfp   M	          z  _  pR  $z  ^     z  F   
    x       
  X      X   
	  Y  $   Y   
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    A    0    A    r 
        $r   	  / r         0    A    0    A    0    A    0    A    G        !r       x   ? `  !  ?          A        A        A   #
      #	      #       G        z    @  $r      r         $r      r         G         s        "  r

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   
   #r      #r        r
     A   r     A   r     A   $r      Ay          
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     y      &   ( y      "   ( y       %   h y      !   b $z     z  a  pb  $z       / z   `  pfp   M	          z  _  pR  $z  ^     z  F   
    x       
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  [  $     Y     [    	               ( 	     h      h     h     h     h     h      b z  b  pR  0    A   ď 0    A   !t  ?   O !t  ?   #t  ?   z    @  0    A     r     A   0    A    0    A            " 0	    A    0
    A    0    A    #	   	   #
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   #       
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	  ]  $  !"        !"        !"        	      M	          z  \   >r        >r        z  ]     x 2v        x2v       y      y      y     y     My          Gy    y            y            y            y            y            y            y            y            y            y            y            y            y            y            y            $v 
     y       &   ( y      "   ( y      %   h y      !   b $z       z   a  pb  $z     / z  `  pfp   M	          z  _  pR  $z  ^    z  F   
    x       
 X     X   
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 Z         "  Z   
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    A    z		    A  O 0    A    #z	
   	    0    A    #z  	    $      #t  ?   0    A     r     A   x   ? @  $t  ?   G  0       z      $r      $      Ay          
 \    0    A   0    A    
	 ]   $   0    A    $      	      M	          z \    >r        >r        z ]     x 2v        x2v       y      y      y     y     My          Gy    y            y            y            y            y            y            y            y            y            $v 
     y      &   ( y      "   ( y       %   h y      !   b $z     z  a  pb  $z       / z   `  pfp   M	          z  _  pR  $z  ^     z  F   
    x       
  X    
  X   
  Z    
	  Y  $   Z     Y   	      
  [  $     [    

     	     (     h      h     h     b 
  \     
	  ]  $   0
    A    $     !t  ?   O 0    A    r     A   0    A    0    A    $      0    A    	      M	          z  \   >r        >r        z  ]     x 2v        x2v       y      y      y     y     My          Gy    y            y            y            y            y            y            y            y            y            y            $v 
     y       &   ( y      "   ( y      %   h y      !   b $z       z   a  pb  $z     / z  `  pfp   M	          z  _  pR  $z  ^    z  F   
    x       
 X     X   
	 Y   $   Y    
 Z    	       Z         
 [   $       "  [           	                     h     h     b Ey         0	    A   ď 0
    A    z		    A  O 0    A    #z	
   	    $      #z	  	    0    A    0    A     r	     A    r     A   x   ? @  $t  ?   G  0       z      $r      $      Ay          
 \    0    A   0    A    
	 ]   $   0    A    $      	      M	          z \    >r        >r        z ]     x 2v        x2v       y      y      y     y     My          Gy    y            y            y            y            y            y            y            y            y            $v 
     y      &   ( y      "   ( y       %   h y      !   b $z     z  a  pb  $z       / z   `  pfp   M	          z  _  pR  $z  ^     z  F   
    x       
  Z      Z   
  X    
  X   
  [  $  
	  Y  $    [     Y    	      	         ( 

    h                 $     O 0    A   0
    A   0    A   Ə  r     A   
  \     0    A    
  ]  $   $      0    A    	      M	          z  \   >r        >r        z  ]     x 2v        x2v       y      y      y     y     My          Gy    y            y            y            y            y            y            y            y            y            y            y            $v 
     y      &   ( y      "   ( y       %   h y      !   b $z     z  c  pb  $z       / z   b  pfp   M	          z  a  pR  $z  `     z  F   
    x       
  X      X   
  Y  $    Y    	          x    ?     $t      x	    ?     0    A   ʏ #x  C   O `{d 0
 B $t   ?    x;  A   x

;  A    x	;  A   #x  C   #x
  C   #x  C    $t   ?   x    ?     `{e 0 B `{e 0 B `{e 0 B 
  ^      x;  A   
	  _  $    x;  A   x;  A    x;  A   	      M	          z  ^   >r        >r        z  _     x 2v        x2v       y      y      y     y     My          Gy    y            y            y            y            y            y            y            y            y            y            y            y            y            y            $v 
     y      &   ( y      "   ( y       %   h y      !   b $z     z  _  pb  $z       / z   ^  pfp   M	          z  ]  pR  $z  \     z  F   
    x       
  X      X   
	  Y  $    Y    	      
         (      h     b z  a  pR  $     O 0
    A    

  Z     0    A    z `    A   0    A    z `    A   
  [  $  !        0    A     z `    A   !        !        	 
     M	          z  Z   >r        >r        z  [     x 2v        x2v       y      y      y     y     My          Gy    y            y            y            y            y            y            y            y            y            y            y            y            y            $v 
     y      &   ( y      "   ( y       %   h y      !   b $z     z  `  pb  $z       / z   _  pfp   M	          z  ^  pR  $z \     z  F   
    x      
 X     X   
	 Y  $   Y    	                (      h     b $z  ]     x	       
  Z     
  [  	$  0    A    0    A    x>  A  O 0    A   #xE?    $
      0
    A    #xx=     r

     A   !v
 a     z 
 a      z b    A   r        x   ? @  x  ?    $      	      M	          z  Z   >r        >r        z  [  	   x 2v        x2v       y      y      y     y     My          Gy    y            y            y            y            y            y            y            y            y            y            y            y            y            y            y            $v 
     y      &   ( y      "   ( y       %   h y      !   b $z     z  `  pb  $z       / z   _  pfp   M	          z  ^  pR  $z \     z  F   
    x      
 X     X   
	 Y  $   Y    	                (      h     b z  c  pR  $z  ]     x	       
  Z     
  [  	$  $
     O 0    A    0    A   z  a    !v a      0
    A   z  a    !v a       z b    A   0    A    z 
 a    !v

 a       z b    A   r         z

 b    A   r        !B        r
       !B        !B        	      M	          z  Z   >r        >r        z  [  	   x 2v        x2v       y      y      y     y     My          Gy    y            y            y            y            y            y            y            y            y            y            $v 
     y      &   ( y      "   ( y       %   h y      !   b $z     z  `  pb  $z       / z   _  pfp   M	          z  ^  pR  $z \     z  F   
    x      
 X     X   
 Y  $   Y    	          $z  ]     x         $r      x	       0    A   ʏ !v a     Oz  a     
  Z      z b    A   
  [  	$  r        x   ? @  x  ?    	      M	          z  Z   >r        z  [  	   y     y      y     y     My          Gy    y            y            y            y            y            y            y            y            y            y            y            y                                                                                                  @                                                                
                                                         p         M                 :                     8                                   7      p                                                  Y      p                !                                         p                !                !                  o     p                "                "                       p                8#                #                       p                #                $                       p                $                %                       p                P%                &                       p                &                '                       p                &                (                  9     p                '                )                       p                T(                *                      p                ()                                   G  	                   8)                                 j  	                   )                                                       *      \                                                  d-                                   '                    .                !                                      |0                "                  A                    2                #                                      3                $                  D                     5                %                                      6                &                  P                    D8                '                                      9                (                                      \;                )                                      <                *                  @                     >               M                                       E               P                 N                    J                Q                                     O                R                 f                    S                S                                     X                T                 f                    \               U                                      a                V                 v                     e               W                                     i               X                                      n               Y                       @|                                                 *                      xG      xG                   @|                                           